Semiconductor (SC) devices are often encapsulated in molded plastic. The molded plastic surrounds and protects the semiconductor die, supports the bonding wires and external leads and imparts ruggedness and shock resistance to the device. Plastic packaged devices are widely used. FIG. 1 shows a simplified schematic cross-sectional view through prior art molded plastic package 20 containing semiconductor (SC) die 22. SC die 22 is conveniently but not essentially mounted on heatsink 23. Metal contact regions 24-1, 24-2 (collectively 24) are provided on SC die 22 to which external leads 26-1, 26-2 (collectively 26) are coupled by wirebonds or other means 25-1, 25-2 (collectively 25). Conductors and interconnections (e.g., metal traces) 31 on die surface 32 are also shown. Plastic encapsulant 27 is molded around SC die 22, conductors 31, wirebond pads 24, wirebonds 25, inner portions 28-1, 28-2 (collectively 28) of external leads 26, so that, in this example, lower surface 21 of heatsink 23 remains exposed on the lower face of package 20, but having surface 21 exposed is not essential. While plastic encapsulation, such as is illustrated in FIG. 1 and equivalents, is widely used, it suffers from a number of disadvantages and limitations well known in the art. Among these are that plastic encapsulation 27 surrounding SC die 22 and leads 25 and 28 and covering conductors 31 has a significantly higher dielectric constant εe and loss tangent δe than does air or vacuum. For example, commonly used plastic encapsulants for semiconductor devices often have dielectric constants εe in the range 3.5 to 5.0 and loss tangents δe in the range 0.005 to 0.015 for the frequency ranges of interest. These are sufficient to cause significant degradation of performance, especially at high frequencies and high voltages. Fringing electric field 29 (created when voltage is applied) extends into plastic encapsulant 27 between various conductors 31 and 24 on surface 32 of SC die 22. This results in capacitive coupling (e.g., “cross-talk”) and power loss (e.g., heat dissipation) in encapsulation 27. These increase as the dielectric constant εe and loss tangent δe of encapsulation 27 increase. Such cross-talk and loss are undesirable.
In the prior art, the capacitive coupling and loss associated with this fringing electric field extending outside of the SC die has been mitigated or avoided by, for example: (i) using a Faraday shield (not shown) over the die, and/or (ii) using hollow ceramic or metal packages that provide an air or vacuum space over the die sensitive surface with conductors 24, 31 and also usually around the wirebonds and inner package leads. A Faraday shield constrains the fringing fields but at the cost of additional die complexity due to the additional conductor and masking layers required. A vacuum or airspace package is illustrated in FIG. 2, which shows hollow package 30 having air or vacuum space 37 surrounding die 32. Die 32 is mounted on, for example, metal, ceramic or plastic base 33-1 to which are attached external leads 36-1, 36-2 (collectively 36). Wirebonds or other connections 35-1, 35-2 (collectively 35) couple bonding pads 34-1, 34-2 (collectively 34) on die 32 to inner portions 38-1, 38-2 (collectively 38) of package leads 36-1, 36-2 (collectively 36). Cap 33-2 is placed over substrate 34, die 32, wirebonds or other connections 35 and inner portions 38 of package leads 36. Having air or vacuum space 37 around die 22 means that fringing electric field 39 is not in contact with any encapsulant. Therefore, an increase in coupling capacitance and/or loss caused by a plastic encapsulant in contract with the die surface and the various conductors is avoided. The dielectric constant εo and loss tangent δo of air or vacuum are low and so cross-talk and dielectric loss are minimized. However, such hollow packages are significantly more expensive and often not as rugged as plastic encapsulation. Wirebonds or other connections 35 can become detached if the finished device is subjected to large acceleration forces.
Thus, there continues to be a need for improved semiconductor devices and methods that provide plastic encapsulated devices with reduced encapsulation related capacitive cross-talk and loss. Accordingly, it is desirable to provide improved semiconductor devices with plastic encapsulation having lower dielectric constant εbl and/or loss tangent δbl material in contact with the die surface. In addition, it is desirable that the improved plastic encapsulation materials, structures and methods allow a substantially solid structure to be formed surrounding the semiconductor die, die leads and bonding wires so as to provide a mechanically rugged package. It is further desirable that the improved devices be achieved using fabrication technology already available on or easily added to a typical semiconductor device manufacturing line so that only minor modification of the manufacturing process is required. It is still further desirable that these advantages be obtained at low cost. Other desirable features and characteristics of the invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.